February 2010 – Reloading Process [0%]
February will be a month of changes to make the base of the rest of the year. Right now I’m configuring a calendar of study to make time for my networking studies [CCNA]. In the college I’m in partials exams, it makes a hard time of study. Soon I will be publishing notes of my studies in route to my CCNA certification.
~mφxαsm
Status Update January – 2010
Well this month i was so lazy about the course to my first goal but i don’t lose the focus of my goal. Since I’m in the university too and the subjects take a lot of my time of study. Now I need to organize my study to make space for my CCNA studies and look how I will get the money for the exam because the mother money support …. well what I can tell you? shit happens!. Thats all for now.
~mφxαsm
Digital Logic – Volume 01 – (1-4)
Intro
- Reproducibility of results.
- Ease of design.
- Flexibility and functionality.
- Programmability.
- Speed.
- Economy
- Constant technological advancement.
AND Gate
Mathematical notation: X = AB X = AB

This is characterized in that has only 1 to its output when all inputs are 1. The determinant value of this gate is 0 since there is a 0 as the input will output 0.
This a AND gate demonstration.
OR Gate
Mathematical notation : X = A+B

The OR gate is 1 to its output when any of its inputs are 1. The determinant of the OR gate is 1: a 1 in an entry immediately determinesa 1 to the exit.
This a OR gate demonstration.
NOT Gate
Mathematical notation : X = X`
The NOT gate is a unitary operator is therefore not decisive. It is known as an investor, denial. A variant of mathematical notation is a bar over the variable and in some technical manuals manufacturers usually put a # after the variable name to show his denial.
This a NOT gate demonstration.
NAND Gate
Mathematical notation: X = A`.B` X = (AB)`

The NAND gate is the negation of the exit gate. Hence its output is 0 only when all its inputs are 1. The determinant of the NAND gate is 0: a 0 in an entry immediately determines a 1 to the exit.
This a NAND gate demonstration.
NOR Gate
Mathematical notation : X = (A+B)`

The NOR gate is the negation of the OR gate output. Hence its output is 0 when any of its inputs are 1. The determinant of the NOR gate is 1: a 1 in an entry immediately determines a 0 to the exit.
This a NOR gate demonstration.
XOR Gate
Mathematical notation : S = A ⊕ B.

The XOR gate is 1 to its output when its inputs are different. No conclusive. The XOR gate is called an odd function for the gate to generate a 1 to its output must be an odd number of 1s in its inputs. This statement is very useful in analyzing more XOR gates of two inputs.
This a XOR gate demonstration.
XNOR Gate
Mathematical notation : S = X ʘ Y.

The XNOR gate is 1 to its output when its inputs are equal. No conclusive. The XNOR gate is called for even function for the gate to generate a 1 to its output must have an even number of 1s in its inputs. This statementis very useful in analyzing XNOR gates more than two entries.
This a XNOR gate demonstration.


